Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms
We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip.
1 Online-Ressource (XIV, 186 Seiten)
9781402048265, 9789048172023, 9789048108800, 9781402048258, 1402048262, 9048172020, 9048108802, 1402048254
612621042
Foreword. Preface.- 1. Introduction.- 2. Embedded SOC Applications.- 3. Classification of Platform Elements.- 4. System Level Design Principles.- 5. Related Work.- 6. Methodology Overview.- 7. Unified Timing Model.- 8. MP-SOC Simulation Framework.- 9. Case Study.- 10. Summary.- Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework.- List of Figures. List of Tables. References.- Index.