The Designer's Guide to VHDLMorgan Kaufmann, 2010. gada 7. okt. - 936 lappuses VHDL, the IEEE standard hardware description language for describing digital electronic systems, has recently been revised. The Designer's Guide to VHDL has become a standard in the industry for learning the features of VHDL and using it to verify hardware designs. This third edition is the first comprehensive book on the market to address the new features of VHDL-2008.
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Saturs
1 | |
31 | |
65 | |
95 | |
137 | |
Chapter 6 Subprograms | 207 |
Chapter 7 Packages and Use Clauses | 245 |
Chapter 8 Resolved Signals | 267 |
Chapter 16 Files and InputOutput | 499 |
A Package for Memories | 535 |
Chapter 18 Test Bench and Verification Features | 559 |
Chapter 19 Shared Variables and Protected Types | 585 |
Chapter 20 Attributes and Groups | 603 |
Chapter 21 Design for Synthesis | 633 |
System Design Using the Gumnut Core | 669 |
Chapter 23 Miscellaneous Topics | 733 |
Chapter 9 Predefined and Standard Packages | 293 |
A Pipelined Multiplier Accumulator | 337 |
Chapter 11 Aliases | 355 |
Chapter 12 Generics | 365 |
Chapter 13 Components and Configurations | 417 |
Chapter 14 Generate Statements | 449 |
Chapter 15 Access Types | 479 |
Standard Packages | 793 |
VHDL Syntax | 841 |
Answers to Exercises | 859 |
References | 889 |
Index | 891 |
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actual alias allows architecture body array associated attribute begin behavioral bit_vector block boolean called changes Chapter character clock complex component condition configuration constant contains conversion count declaration defined delay described directive downto driver element end process entity error example executed expression formal function function function identifier implementation indication inout input instance instantiation instruction integer label logic loop memory natural object operand operations output package parameter perform port port map procedure protect record refer represent reset result return boolean return unresolved round shown signal signed simulation specify statement std_ulogic string structure style subprogram subtype syntax rule tool true ufixed ulogic unit unresolved float unresolved sfixed unsigned variable vector versions VHDL wait width write