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" Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. "
Leakage in Nanometer CMOS Technologies - 78. lappuse
laboja - 2006 - 308 lapas
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Low Power Methodology Manual: For System-on-Chip Design

David Flynn, Rob Aitken, Alan Gibbons, Kaijian Shi - 2007 - 300 lapas
...hierarchical sizing based on mutual exclusive discharge patterns", in Proc. Design Automation Conference, 1998 M. Anis, S. Areibi and M. Elmasry, "Design and optimization of multi-threshold CMOS (MTCMOS) circuits", IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 2003 M. Powell, S.-H Yang, et. al.,...
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Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low ...

David Chinnery, Kurt Keutzer - 2008 - 388 lapas
...Q., and Vrudhula, S., "Algorithms for Minimizing Standby Power in Deep Submicrometer, Dual-Vt CMOS Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 3, 2002, pp. 306-318. Chapter 5 METHODOLOGY TO OPTIMIZE ENERGY OF COMPUTATION FOR SOCS Jagesh...
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Modern Circuit Placement: Best Practices and Results

Gi-Joon Nam, Jingsheng Jason Cong - 2007 - 324 lapas
...Conference, 1991, pp. 427-431 42. W.-J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14(5), pp. 349-359, 1995 43. T. Taghavi, X. Yang, BK Choi, M. Wang and M. Sarrafzadeh, "DRAGON2005:...
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VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth ...

Ricardo Reis, Adam Osseiran, Hans-Joerg Pfleiderer - 2007 - 344 lapas
...L. Milor and AL Sangiovanni-Vincentelli, "Minimizing Production Test Time to Detect Faults in Analog Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., Vol. 13, No. 6, pp 796-, June 1994. 19. P. Varma and S. Bhatia, "A Structured Test Re-Use Methodology for...
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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Manoj Sachdev, José Pineda de Gyvez - 2007 - 328 lapas
...pp. 382-385, 1997 53. PN Variyam and A. Chatterjee, "Specification-Driven Test Generation for Analog Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems," vol. 19, no. 10, pp. 1189-1201, October 2000. 54. V. Vishvanathan and A. Sangiovanni-Vincentelli, "Diagnosability...
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Substrate Noise Coupling in RFICs

Ahmed Helmy, Mohammed Ismail - 2008 - 119 lapas
...Meyer, "Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits", IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 17, n. 4, pp. 305-315, April 1998. 17. DM Young, Iterative Solution of Large Linear Systems, Academic...
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On-Chip Communication Architectures: System on Chip Interconnect

Sudeep Pasricha, Nikil Dutt - 2010 - 544 lapas
...May 1996, pp. 637-640. [57] M. Borah, RM Owens and MJ Irwin, "Transistor sizing for low power CMOS circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 6, June 1996, pp. 665-671. [58] R. Rogenmoser and H. Kaeslin, "The impact of transistor sizing...
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