Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 61.
... tools. One can rightly talk about the verification gap (i.e. growing proportion of verification time and effort in the overall development cycle1), or even about the verification crisis. In today's complex digital circuit designs ...
... tools. Once the assertion language is learned, adding as- sertions to a design to perform verification requires low overhead since assertions are text-based commands. Furthermore, assertions can be added incrementally as needed or as ...
... tool [103]. The original assertion language that served as the foundation for PSL was actually developed by IBM and was called “Sugar”. The FoCs tool was originally intended for simulation use; however, the circuit checkers that are ...
... tool [29]. Automatic generation of checkers from assertions is much more advantageous than designing checkers by hand. For one, a single line of PSL can sometimes imply hundreds of lines of HDL code. Maintaining checker code in HDL form ...
... tool from IBM, and we show that the MBAC checker gen- erator produces smaller and faster circuits that offer the correct assertion behavior while supporting all simple subset operators. Chapter 9 is devoted to checker generation for ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |