Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 51.
... techniques, the methodol- ogy and usage aspects of assertions are also explored in several instances. The principal set of problems addressed in this book is presented here by means of distinct challenges, to closely relate to the ...
... techniques used in developing the checker generator can further be applied to areas as diverse as hardware-accelerated pro- tein matching (Subsection 8.4.1) and network intrusion detection, where hardware implementations of regular ...
... techniques with assertions. These assertion statements can also be used as primitives in contract-based programming [128] and related para- digms. By now, assertions are widely used in software development. According to an- other great ...
... techniques over concurrent systems are: deadlocks and live- locks, under-specification (unexpected conditions), over ... technique used extensively in the formal verification of both hardware and software systems. A definition of model ...
... techniques for constructing hardware checkers for modern assertion languages. Although the major portion of this book is centered upon PSL assertions, an entire chapter is devoted 16 2 Assertions and the Verification Landscape Uses of ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |