Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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6.10. rezultāts no 81.
... specification for design teams, and can often be finished only after the product is deployed in its intended environment. Once the overall specification is completed, design teams face a variety of de- sign verification and ...
... specifications. In another view, assertions can be seen as an executable specification [108], or a computable specification, when interpreted by verification tools. Once the assertion language is learned, adding as- sertions to a design ...
... specification stage to allow the formal documentation of requirements. More details on various uses of asser- tions, including those used during the specification phase, appear in a very insightful book on assertion-based design [75] ...
... specification and de- sign phases can have important benefits throughout the remainder of the design cycle. One example of this is when separate design and verification teams work to- gether to correct the errors. Having a formally ...
... specification can sometimes change during the development. Furthermore, if complex checkers are coded by hand they ... specifications respectively, all are implemented 6 1 Introduction Book Objectives.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |