Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 46.
... Simulation Emulation Formal On-Line Monitoring Dynamic Verification Static Verification Assertion Checkers in ... simulated, it is tempting to emulate or accelerate them by hard- ware, where the implicitly parallel nature of logic ...
... simulation use; however, the circuit checkers that are produced can also be synthesized in hardware. As witnessed in the history of publications (in chronological order) [25–32], the checker generator developed in this book has ...
... simulation acceleration, to software-only interpreta- tion of assertions as used in traditional simulators, and can even extend into formal verification by allowing certain types of properties to be used in model checkers that do not ...
... simulation, emulation and formal verification are overviewed. Assertion checkers and checker generators, two central themes in this book, are also presented. An introduction to temporal logic is also performed, given the strong ...
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Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |