Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
1.–5. rezultāts no 46.
... simulation, formal verification, emulation, post-silicon debug- ging, and hardware runtime monitoring can use these checkers. With the emergence of assertion language and library standards – such as the IEEE SystemVerilog As- sertions ...
... simulation, emulation). The checkers are designed with the goals that: (1) they should require few hardware resources when implemented in a circuit form, and should be fast, to allow high clock speeds; and (2) that they continually ...
... Simulation and Emulation Semantics . Basic Techniques Behind Assertion Checkers . 3.1 Background 3.1.1 Regular Expressions and Classical Automata 3.1.2 Automata in Model Checking . . . . 7 9 13 13 16 20 24 27 28 33 37 37 38 44 3.2 ...
... 1 The verification gap is nicely illustrated on the cover page of the book “Scalable Hardware Verification with Symbolic Simulation” [19]. have very different meanings . The first assertion's primitives b 2 1 Introduction.
... learn are well understood by homemakers when providing for their families: quality costs, but it pays over time. Fabrication Specification Design Prototype Silicon Production Silicon Debug Simulation Emulation 1.1 Context and Motivation 3.
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
Citi izdevumi - Skatīt visu
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |