Digital Systems and ApplicationsVojin G. Oklobdzija CRC Press, 2017. gada 19. dec. - 992 lappuses New design architectures in computer systems have surpassed industry expectations. Limits, which were once thought of as fundamental, have now been broken. Digital Systems and Applications details these innovations in systems design as well as cutting-edge applications that are emerging to take advantage of the fields increasingly sophisticated capabilities. This book features new chapters on parallelizing iterative heuristics, stream and wireless processors, and lightweight embedded systems. This fundamental text
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No grāmatas satura
6.10. rezultāts no 72.
1-26. lappuse
... operations in parallel and in lockstep. Usually the local memories of the PE array are mapped onto the central ... operation, such as an add can scale with the precision of the operands, making them well suited to tasks such as ...
... operations in parallel and in lockstep. Usually the local memories of the PE array are mapped onto the central ... operation, such as an add can scale with the precision of the operands, making them well suited to tasks such as ...
1-30. lappuse
... operation using a separate collection of instruction bits. They are also expressive, relaying much useful information from software to hardware. When a compiler or programmer specifies a vector instruction, they indicate that all of the ...
... operation using a separate collection of instruction bits. They are also expressive, relaying much useful information from software to hardware. When a compiler or programmer specifies a vector instruction, they indicate that all of the ...
1-31. lappuse
... operation will find its source and destination operands located within the same lane, which dramatically reduces interconnect costs. Vector supercomputers can have as many as 16 parallel 64-bit lanes in each CPU. For example, the NEC SX ...
... operation will find its source and destination operands located within the same lane, which dramatically reduces interconnect costs. Vector supercomputers can have as many as 16 parallel 64-bit lanes in each CPU. For example, the NEC SX ...
1-37. lappuse
... operations when the ordering implicit in the basic operations is not sufficient. 1.4.2.1.1 Thread Granularity and Management Thread-level parallelism (TLP) is more coarse-grained than ILP, and has wide variance in granularity. We ...
... operations when the ordering implicit in the basic operations is not sufficient. 1.4.2.1.1 Thread Granularity and Management Thread-level parallelism (TLP) is more coarse-grained than ILP, and has wide variance in granularity. We ...
1-38. lappuse
... operation serves as a synchronizing point. Apart from the join, other explicit synchronization operations can be introduced using locks and barriers. Computation inside each thread is based on sequential control flow. This thread ...
... operation serves as a synchronizing point. Apart from the join, other explicit synchronization operations can be introduced using locks and barriers. Computation inside each thread is based on sequential control flow. This thread ...
Saturs
1-1 | |
Chapter 2 System Design | 2-1 |
Chapter 3 Architectures for Low Power | 3-1 |
Chapter 4 Performance Evaluation | 4-1 |
Embedded Applications | 4-47 |
Chapter 5 Embedded SystemsonChips | 5-1 |
Chapter 6 Embedded Processor Applications | 6-1 |
Chapter 7 An Overview of SoC Buses | 7-1 |
Chapter 15 Circuits for HighPerformance IO | 15-1 |
Chapter 16 Algorithms and Data Structures in External Memory | 16-1 |
Chapter 17 Parallel IO Systems | 17-1 |
Chapter 18 A Read Channel for Magnetic Recording | 18-1 |
Operating System | 18-113 |
Chapter 19 Distributed Operating Systems | 19-1 |
New Directions in Computing | 19-15 |
A Strategically Programmable System | 20-1 |
Signal Processing | 7-17 |
Chapter 8 Digital Siganl Processing | 8-1 |
Chapter 9 DSP Applications | 9-1 |
Chapter 10 Digital Filter Design | 10-1 |
Chapter 11 Audio Siganl Processing | 11-1 |
Chapter 12 Digital Video Processing | 12-1 |
Chapter 13 LowPower Digital Signal Processing | 13-1 |
Communications and Networks | 13-19 |
Chapter 14 Communications and Computer Networks | 14-1 |
InputOutput | 14-19 |
Chapter 21 Reconfigurable Processors | 21-1 |
Chapter 22 Roles of Software Technology in Intelligent Transportation Systems | 22-1 |
Chapter 23 Media Signal Processing | 23-1 |
Chapter 24 Internet Architectures | 24-1 |
Chapter 25 Microelectronics for Home Entertainment | 25-1 |
Chapter 26 Mobile and Wireless Computing | 26-1 |
Chapter 27 Data Security | 27-1 |
Index | I-1 |
Back cover | I-21 |
Bieži izmantoti vārdi un frāzes
addition algorithm allows applications approach architecture audio bits block branch buffer cache called channel clock communication complexity components core cycle decoder defined delay dependencies described detector devices disk drive effect efficient elements equalizer error example execution fetch field Figure filter frequency function given hardware implementation important increased input instruction interface issue logic loop mapping means measured memory method multiple noise operation optimization output packed parallel performance phase position possible prediction problem processing processor recording reduce referred rename response result sample sequence shift shown in Fig shows signal simple simulator single solution space specific structure subwords techniques threads typical unit
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