Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 92.
... monitoring etc., and in the process unifies the treatment of all these areas. The tool devised in this work generates more efficient and more correct checkers, while at the same time it more thoroughly supports the PSL and SVA language ...
... monitoring • Chapter 8: Experimental results for PSL checkers, benchmarking of real and syn- thetic assertions, experiments in creating hardware-accelerated protein matching checkers • Chapter 9: Automata construction for SystemVerilog ...
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring Marc Boulé, Zeljko Zilic. manuals ([108] and [107]). Readers wanting to learn exact semantics of operators can (and should) complement their reading ...
... Monitoring Activity ... 7.4.3 Signaling Assertion Completion . 155 156 160 162 163 163 165 7.4.4 Assertion and Cover Counters . 167 7.4.5 Hardware Assertion Threading 168 7.5 Checkers in Silicon Debug and On - Line Monitoring 172 7.5.1 ...
For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring Marc Boulé, Zeljko Zilic. Fabrication Specification Design Prototype Silicon Production Silicon Debug Simulation Emulation Formal On-Line Monitoring ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |