Leakage in Nanometer CMOS TechnologiesSiva G. Narendra, Anantha P. Chandrakasan Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. |
No grāmatas satura
6.–10. rezultāts no 86.
3. lappuse
Siva G. Narendra, Anantha P. Chandrakasan. reduce the impact leakage will have on the design margin. Techniques such ... reduction solutions will also be discussed. While administration is not specifically discussed in the book, this is ...
Siva G. Narendra, Anantha P. Chandrakasan. reduce the impact leakage will have on the design margin. Techniques such ... reduction solutions will also be discussed. While administration is not specifically discussed in the book, this is ...
13. lappuse
... reduction and adaptation techniques that directly help minimize the impact of leakage and parameter variation, (ii) prediction methodologies that help understand the source and ... leakage reduction. Also, uses of 1. Taxonomy of Leakage 13.
... reduction and adaptation techniques that directly help minimize the impact of leakage and parameter variation, (ii) prediction methodologies that help understand the source and ... leakage reduction. Also, uses of 1. Taxonomy of Leakage 13.
14. lappuse
Siva G. Narendra, Anantha P. Chandrakasan. leakage reduction techniques for active leakage reduction. Also, uses of multi-performance transistors for power reduction are described in Chapter 8. Chapter 9 covers impact of leakage and ...
Siva G. Narendra, Anantha P. Chandrakasan. leakage reduction techniques for active leakage reduction. Also, uses of multi-performance transistors for power reduction are described in Chapter 8. Chapter 9 covers impact of leakage and ...
21. lappuse
... leakage refers to subthreshold leakage, unless otherwise explicitly mentioned. One of challenge with technology scaling is the rapid increase in subthreshold leakage power due to V, reduction. Should the present scaling trend continue ...
... leakage refers to subthreshold leakage, unless otherwise explicitly mentioned. One of challenge with technology scaling is the rapid increase in subthreshold leakage power due to V, reduction. Should the present scaling trend continue ...
22. lappuse
... leakage reduction factor is also discussed. The derived model for leakage reduction depends on fundamental transistor parameter. This makes the model viable to predict potential leakage savings using stack effect techniques in future ...
... leakage reduction factor is also discussed. The derived model for leakage reduction depends on fundamental transistor parameter. This makes the model viable to predict potential leakage savings using stack effect techniques in future ...
Saturs
Chapter 6 | 141 |
Chapter 7 | 163 |
Chapter 8 | 200 |
L | 209 |
Chapter 9 | 211 |
Chapter 10 | 234 |
VVV0xW+2+ 20 1 | 236 |
Periphery | 254 |
Chapter 4 | 77 |
11 | 81 |
Vdd I t I | 96 |
botas bbarabosse cseldk14keyb long sandsly | 102 |
Chapter 5 | 105 |
6 | 108 |
aget | 121 |
Chapter 11 | 257 |
i | 269 |
i | 274 |
Chapter 12 | 281 |
B | 291 |
Figure 129 Carbon nanotube structures | 298 |
Citi izdevumi - Skatīt visu
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Ierobežota priekšskatīšana - 2006 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2005 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
achieved active mode adaptive additional allows applied approach becomes biasing block body bias capacitance cause cell channel length Chapter charge chip circuit clock CMOS compared critical defective delay depends described devices drain drive dynamic effect energy example Figure frequency higher IDDQ IEEE impact implementation improve increase input junction larger leakage current leakage power leakage reduction limit logic lower measured microprocessor minimize MOSFET MTCMOS needed NMOS node noise operation output oxide parameter path penalty performance PMOS power gating power supply power switch presented reduce leakage reduced savings scaling scheme selected shown in Figure shows signal sleep transistor smaller solution speed SRAM stack standby mode sub-threshold leakage substrate supply voltage techniques temperature threshold voltage tunneling turned variation virtual width
Populāri fragmenti
42. lappuse - Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, and M. Bohr, "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers ofCu interconnects
78. lappuse - Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
42. lappuse - Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," International Symposium on Low Power Electronics and Design, pp.
202. lappuse - 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold- Voltage CMOS," IEEE Journal of Solid-State Circuits, Vol.
143. lappuse - T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako. M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz.
79. lappuse - Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Design.
79. lappuse - S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, A 1-V high-speed MTCMOS circuit scheme for power-down application circuits, IEEE J.
143. lappuse - K. Seta, H. Hara, T. Kuroda, M. Kakumu, and T. Sakurai, "50% active-power saving without speed degradation using standby power reduction (SPR) circuit,
143. lappuse - A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme," IEEE Journal of Solid-State Circuits, vol.
Atsauces uz šo grāmatu
Low Power Methodology Manual: For System-on-Chip Design David Flynn,Rob Aitken,Alan Gibbons,Kaijian Shi Ierobežota priekšskatīšana - 2007 |
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |