Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 90.
... Language Compilation 255 10.2.4 Testing the Checkers 256 10.2.5 Beyond RTL Assertion Languages . 257 A Example for Up - Down Counter .. 259 References . 265 Index 275 Acronyms ABD ABV ASIC AMBA The following is a short Contents xvii.
... Language ( properties ) Field Programmable Gate Array Hardware Description Language Integrated Circuit Institute of Electrical and Electronics Engineers Intellectual Property Linear Temporal Logic Nondeterministic Finite Automaton OBE ...
... Language Random Access Memory RE Regular Expression RTL Register Transfer Level SERE SOC System On Chip SV System Verilog SVA Sequential Extended Regular Expression System Verilog Assertions Chapter 1 Introduction Abstract This chapter ...
... language, free of the am- biguities inherent to natural language specifications. In another view, assertions can be seen as an executable specification [108], or a computable specification, when interpreted by verification tools. Once ...
... Language (HDL) in use today [55], and is certainly expressive enough in describing most hardware endeavors. The Verilog language is used in this work as the underlying language for expressing circuit designs, thus the Verilog HDL and ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |