The Designer's Guide to VHDLElsevier, 2001. gada 5. jūn. - 759 lappuses Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. |
No grāmatas satura
6.–10. rezultāts no 89.
... input sel; four data inputs d0, d1,d2 and d3; and a data output z. The data inputs and outputs are of the IEEE standard-logic type, and the select input is of type sel_range, which we assume to be declared elsewhere as type sel_range is ...
... input that, when '1', causes the count output to be reset to zero. The output stays at zero as long as the reset input is '1' and resumes counting on the next clock transition after reset changes to '0'. The revised entity declaration ...
... input stimuli and execution paths leading to the assertion statement. If we have a number of assertion statements throughout a model, it is useful to know which assertion is violated. We can get the simulator to provide extra ...
... input and a data output of type real and a clock input of type bit. When the clock changes from '0' to '1', the data input is sampled, stored and transmitted through to the output. Let us suppose that the clock input must remain at '1 ...
... input clk changes to '1'. So long as d is '0', the loop continues executing. When d is '1', the loop exits. 6. [➀ ... inputs, data_in, lower and upper; an integer output, data_out; and a bit output, out_of_limits. The data_out output ...
Saturs
1 | |
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter 9 Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter D Related Standards | 671 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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