Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 54.
... Formal On-Line Monitoring Dynamic Verification Static Verification Assertion Checkers in: Assertion-Based Verification (ABV) [62, 75] is emerging as the predomi- nant methodology for performing hardware verification. Assertions are high ...
... formal verification by allowing certain types of properties to be used in model checkers that do not support PSL and SVA. The techniques used in developing the checker generator can further be applied to areas as diverse as hardware ...
... formal verification, more specifically in model checking, is also surveyed. This chapter also contains an introduction to classical automata theory and regular expressions, and can be very helpful prerequisites to the automata framework ...
... formal verification are overviewed. Assertion checkers and checker generators, two central themes in this book, are also presented. An introduction to temporal logic is also performed, given the strong foundations of assertion languages ...
... Formal reasoning about such concurrent systems can be performed by modeling the systems at a higher abstraction ... formal reasoning techniques over concurrent systems are: deadlocks and live- locks, under-specification (unexpected ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |