Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
6.–10. rezultāts no 82.
59. lappuse
... example:2 The design description states that when the driver asserts the. 2 This example works backward and is for illustration purposes only. During the course of normal verification, the verification engineer is not “given” a bug ...
... example:2 The design description states that when the driver asserts the. 2 This example works backward and is for illustration purposes only. During the course of normal verification, the verification engineer is not “given” a bug ...
77. lappuse
... example, this chapter builds on the cache design shown in Chapter 2 (see Figure 2.20). Figure 3.3 shows that the protocol component needs to drive five separate signals and buses comprising 77 total bits. In this example, the protocol ...
... example, this chapter builds on the cache design shown in Chapter 2 (see Figure 2.20). Figure 3.3 shows that the protocol component needs to drive five separate signals and buses comprising 77 total bits. In this example, the protocol ...
78. lappuse
... example contains a buffer than can hold up to eight fetch requests concurrently. If at any time during the test case, the generation component (requestor) sends a request to the DUV such that the cache had nine outstanding fetch ...
... example contains a buffer than can hold up to eight fetch requests concurrently. If at any time during the test case, the generation component (requestor) sends a request to the DUV such that the cache had nine outstanding fetch ...
79. lappuse
... example and have multiple concurrent or overlapping interactions and many more control and data signals. Breaking these components apart simplifies the coding of the environment. This structure has other benefits as well: a separate ...
... example and have multiple concurrent or overlapping interactions and many more control and data signals. Breaking these components apart simplifies the coding of the environment. This structure has other benefits as well: a separate ...
90. lappuse
... example. This time the HDL assertion actually protects the physical implementation of the logic. It codifies the assumption that two “select” signals (s1, s2), which drive a pass-gate multiplexer implementation, are to be orthogonal. In ...
... example. This time the HDL assertion actually protects the physical implementation of the logic. It codifies the assumption that two “select” signals (s1, s2), which drive a pass-gate multiplexer implementation, are to be orthogonal. In ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL