Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 59.
... developed in this research is particularly tailored for syn- thesizing assertion checkers that consume the least amount of circuit resources when implemented in hardware. Many design choices and optimizations are performed with the ...
... developed, with an example application in redundancy control. The concept of mixing automata with separate logic gates is introduced in Section 7.3 for imple- menting a more efficient form of the eventually! operator, when compared to ...
... developed, such as determinization and minimization. The conversion of au- tomata to circuit-level checkers is also developed at the end of Chapter 5. The automata construction for all PSL assertion operators is introduced in Chapter 6 ...
... developed to automate the individual synthesis of checkers when grouped in a single Verilog module . Another script was developed to automatically extract and convert the synthesis results into LATEX formatted tables . These scripts ...
... develop and organize the de- bug enhancements, and in particular, the ideas of monitoring completion, adding counters for ... developed using an automata library used in speech recognition at the CRIM (Centre de Recherche Informatique de ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |