Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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6.–10. rezultāts no 76.
45. lappuse
... compiler can target different objective functions such as minimizing the execution time of the compiled code, reducing executable size, improving power or energy behavior of the generated code, and so on. In addition, it is also ...
... compiler can target different objective functions such as minimizing the execution time of the compiled code, reducing executable size, improving power or energy behavior of the generated code, and so on. In addition, it is also ...
61. lappuse
... compiler. To accomplish programmable communication, each tile has a router. The compiler programs the routers on all tiles to issue a sequence of commands that deter- mine exactly which set of wires connect at every cycle. Moreover, the ...
... compiler. To accomplish programmable communication, each tile has a router. The compiler programs the routers on all tiles to issue a sequence of commands that deter- mine exactly which set of wires connect at every cycle. Moreover, the ...
78. lappuse
... compilers [134] and interactive code transformation methodologies, such as, for instance, the data transfer and storage exploration (DTSE) proposed by IMEC [135]. In an NoC environment these tools should focus on removing or reducing ...
... compilers [134] and interactive code transformation methodologies, such as, for instance, the data transfer and storage exploration (DTSE) proposed by IMEC [135]. In an NoC environment these tools should focus on removing or reducing ...
79. lappuse
... compiler , linker , assembler Binary code Simulation , debug , tuning Multiprocessor simulators , debugger , profiler 79 80 abstraction levels. NoC simulation platforms have recently been presented. FIGURE Software development ...
... compiler , linker , assembler Binary code Simulation , debug , tuning Multiprocessor simulators , debugger , profiler 79 80 abstraction levels. NoC simulation platforms have recently been presented. FIGURE Software development ...
87. lappuse
... compiler can try to separate a load instruction from its use , by scheduling inde- pendent instructions between the two , as shown in Figure 4-8 . This technique is known as static scheduling . Alternatively , hardware can reorder ...
... compiler can try to separate a load instruction from its use , by scheduling inde- pendent instructions between the two , as shown in Figure 4-8 . This technique is known as static scheduling . Alternatively , hardware can reorder ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa