Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 69.
... checking circuits is of primary impor- tance when assertion-based verification is to be used in hardware emulation, post- fabrication silicon debugging and on-line monitoring applications. Assertions are often first viewed as a means of ...
... checking, is also surveyed. This chapter also contains an introduction to classical automata theory and regular expressions, and can be very helpful prerequisites to the automata framework and the regular expressions appearing elsewhere ...
... Checking. Assertions have been used in software for many decades. The history of reasoning about programs [114] reveals that the concept of assertions was introduced in 1947 by Herman Heine Goldstine and John von Neumann, where the idea ...
... checking. They are however, a means to instrument the code with non-critical checks that can reveal programming errors during debugging. In most cases, the assertions are not instrumented when a release-mode compilation is per- formed ...
... checking is an automated technique that, given a finite-state model of a system and a logical property, systematically checks whether this prop- erty holds for (a given initial state in) that model. This definition serves equally well ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |