Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 88.
... Assertions and the Verification Landscape 2.1 Origins of Assertions : Software Checking 2.2 2.3 Uses of Assertions in Hardware . . . . Assertion Checkers and Checker Generators 2.4 Assertion Support in Simulators and Emulators 2.5 Checkers ...
... Assertion Checkers 179 8.1 Introduction and Overview . . 179 8.2 Non - synthetic Assertions .. 182 8.3 Evaluating Assertion Grouping 188 8.4 Pre - synthesis Results 191 8.4.2 8.4.1 Experiments with Hardware Protein Matchers Complex ...
... Assertion Checkers in: Assertion-Based Verification (ABV) [62, 75] is emerging as the predomi- nant methodology for performing hardware verification. Assertions are high-level statements built on temporal logic that are added to a ...
... assertions to be used in hardware, a checker generator is re- quired to transform the assertions into circuit-level checkers. Assertions are written in high-level languages and are not suitable for direct implementation in circuit form ...
... checkers for circuit implementations. In one example, a checker that is three or- ders of magnitude smaller in terms of code size was produced, compared to the FoCs tool [29]. Automatic generation of checkers from assertions is much ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |