Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
No grāmatas satura
6.–10. rezultāts no 80.
... Chapters 5, 6 and 9, where the automata framework and the algorithms for converting PSL and SVA into au- tomata, and subsequently into circuits, are developed. Over 20 automata algorithms are developed, and over 30 rewrite rules are ...
... Chapter 6. The results of all challenges are assessed empirically in Chapter 8 and in Section 9.3. In this work, a checker generator is devised with particular uses in verification, silicon debugging and on-line monitoring. The ...
... chapter, where other assertion languages are also mentioned. Chapter 4 contains an introduction to PSL and SVA, where the syntax of these languages is formally presented. An informal explanation of both language's se- mantics is also ...
... Chapter 8 and in Section 9.3 . The ideas of assertion grouping and management of checkers in programmable cores was also contributed by Mr. Chenard . Assertion grouping was also mentioned previously [ 2 ] , 1 By Young, Boebert and Kain ...
... Chapter 7 were originally designed by Mr. Chenard. Jean-Samuel also coded the CPU pipeline and helped work out the related assertion threading example in Section 7.4 (Example 7.4) [28]. The authors would also like to mention the ...
Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
Citi izdevumi - Skatīt visu
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |