Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line MonitoringSpringer Science & Business Media, 2008. gada 1. jūn. - 280 lappuses Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. |
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6.10. rezultāts no 91.
... first viewed as a means of performing, enabling or facilitat- ing the task of hardware verification, hence the term Assertion-Based Verification (ABV). However, to emphasize that assertions should be adopted in the earliest stages of ...
... first assertion's primitives b and p are in type- writer font and are the actual symbols that form the input text for the assertion . Hence , they are interpreted as two single - letter Boolean signals called b and p re- spectively . In ...
... first author gratefully ac- knowledges researchers Morin-Allory and Borrione from the TIMA-VDS group for the invitation and the time spent in the VDS laboratory learning about PSL proofs in PVS. One of the results of this exchange is ...
... first silicon success, leading to more than 60% of total project time for an average IC design being spent after the first IC tapeout. Further, among all possible causes in modern Systems-on-Chip (SOCs), logic/functional bugs are found ...
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Saturs
1 | |
13 | |
Basic Techniques Behind Assertion Checkers | 37 |
PSL and SVA Assertion Languages | 55 |
Automata for Assertion Checkers | 83 |
Construction of PSL Assertion Checkers | 105 |
Enhanced Features and Uses of PSL Checkers | 155 |
Evaluating and Verifying PSL Assertion Checkers | 179 |
Checkers for System Verilog Assertions | 207 |
Conclusions and Future Work | 251 |
A Example for UpDown Counter | 259 |
References | 265 |
Index | 275 |
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Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2010 |
Generating Hardware Assertion Checkers: For Hardware Verification, Emulation ... Marc Boulé,Zeljko Zilic Priekšskatījums nav pieejams - 2008 |