Digital System Clocking: High-Performance and Low-Power AspectsJohn Wiley & Sons, 2005. gada 11. marts - 272 lappuses Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic.
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Saturs
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HighPerformance and LowPower Aspects Chapter 2 Theory of Clocked Storage Elements | 27 |
HighPerformance and LowPower Aspects Chapter 3 Timing and Energy Parameters | 47 |
HighPerformance and LowPower Aspects Chapter 4 Pipelining and Timing Analysis | 63 |
HighPerformance and LowPower Aspects Chapter 5 HighPerformance System Issues | 83 |
HighPerformance and LowPower Aspects Chapter 6 LowEnergy System Issues | 105 |
HighPerformance and LowPower Aspects Chapter 7 Simulation Techniques | 125 |
HighPerformance and LowPower Aspects Chapter 8 StateoftheArt Clocked Storage Elements in CMOS Technology | 155 |
HighPerformance and LowPower Aspects Chapter 9 Microprocessor Examples | 189 |
HighPerformance and LowPower Aspects References | 233 |
HighPerformance and LowPower Aspects Index | 241 |
Citi izdevumi - Skatīt visu
Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija,Vladimir M. Stojanovic,Dejan M. Markovic,Nikola M. Nedovic Ierobežota priekšskatīšana - 2003 |
Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija,Vladimir M. Stojanovic,Dejan M. Markovic,Nikola M. Nedovic Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
Alpha analysis borrowing capacitance captured chip circuit Clk-Q delay clock arrival clock cycle clock distribution network clock driver clock edge clock frequency clock gating clock network clock period clock pulse clock signal clock skew clock uncertainty clocked storage elements clocking energy CMOS Copyright critical path CZMOS D—Q delay data arrival data input DCQm DDQM defined deskewing digital systems driving DTLA-L dual-edge-triggered duty cycle energy consumption example fanout fast paths feedback Figure first stage flip-flop glitch global clock HLFF IEEE implementation increase inverter delay jitter latch-mux leading edge logic gate logical effort LSSD M-SAFF master latch microprocessor minimize NAND gate node noise operation optimal p-MOS parameters performance phase pipeline stages PowerPC 603 precharge processor reduced rising edge SDFF shown in Fig simulation static supply voltage switching technique topology trailing edge transistors transition transparency window triggered VCDL
Populāri fragmenti
240. lappuse - Enhancing Testability of Large Scale Integrated Circuits Via Test Points and Additional Logic,
238. lappuse - Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
236. lappuse - F. Klass et al., A new family of semidynamic and dynamic flip-flops with embedded logic for highperformance processors, IEEE J.
53. lappuse - In order to understand the full effects of delayed data arrival we have to consider a pipelined design where the data captured in the first clock cycle is used as input in the next clock cycle as shown in Fig. 7. Clock Source Combinational logic Clock Destination ,-iH. samphng window Fig. 7. "Time Borrowing...
239. lappuse - Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems", IEEE Journal of Solid-State Circuits, vol.
240. lappuse - CMOS 3-880MHz PLL N/2 Clock Multiplier and Distribution Network with Low Jitter for Microprocessors...
233. lappuse - Clocking Design and Analysis for a 600-MHz Alpha Microprocessor," IEEE Journal of Solid-State Circuits, Vol.
17. lappuse - Clock Parameters: Period, Width, Clock Skew and Clock Jitter Clock jitter represents edge-to-edge variation of the clock signal in time. As such, clock jitter can also be classified as: long-term jitter and edge-to-edge clock jitter, which defines...
103. lappuse - ... from the surrounding stages. Combinational logic of stage 1 takes more time than nominally assigned, and it borrows a portion of the cycle time from stage 2. In general, the storage element may not be completely transparent (ie, data-to-output characteristics are not completely flat).
17. lappuse - Clock jitter represents edge-to-edge variation of the clock signal in time. As such, clock jitter can also be classified as long-term jitter and edge-to-edge clock jitter, which defines the clock signal variation between two consecutive clock edges.
Atsauces uz šo grāmatu
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |
Integrated Circuit and System Design. Power and Timing Modeling ... Lars Svensson,José Monteiro Ierobežota priekšskatīšana - 2009 |