Architecture Design and Validation MethodsEgon Börger Springer Science & Business Media, 2000. gada 6. marts - 357 lappuses This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan. |
Saturs
Modeling and Synthesis of Behavior Control and Data Flow | 1 |
2 Behavioral Synthesis | 3 |
3 HighLevel Control | 15 |
4 Data Flow | 24 |
5 Conclusion | 42 |
Cellbased Logic Optimization | 49 |
3 Algorithms for Library Binding | 52 |
4 Boolean Matching | 60 |
References | 185 |
Machine Assisted Verification | 191 |
2 Logic Verification | 195 |
3 BitVector and WordLevel Verification | 207 |
4 Verification by FixedPoint Calculations | 211 |
5 Verification Techniques for Bounded State Sequences | 218 |
6 Formally Correct Construction of Pipelined Systems | 231 |
References | 238 |
5 Generalized Matching | 78 |
6 Conclusion | 83 |
References | 84 |
New Paradigms for Iteration Free Synthesis | 89 |
2 Flow Components | 92 |
3 Layout Synthesis | 99 |
4 Placement Versus Floorplan Design | 101 |
5 Global Wires | 115 |
6 Wire Planning | 122 |
7 Gate Sizing | 127 |
8 Conclusions | 137 |
Test and Testable Design | 141 |
2 Defect Analysis and Fault Modeling | 143 |
3 External Testing | 155 |
4 SelfTestable SystemsOnChip | 162 |
Models of Computation for System Design | 243 |
Basic Concepts and the Tagged Signal Model | 248 |
3 Common Models of Computation | 261 |
4 Codesign Finite State Machines | 276 |
5 Conclusions | 289 |
References | 292 |
Modular Design for the Java Virtual Machine Architecture | 297 |
2 The Trustful Virtual Machine | 301 |
3 The Defensive Virtual Machine | 313 |
4 The Diligent Virtual Machine | 323 |
5 The Dynamic Virtual Machine | 334 |
6 Related and Future Work | 344 |
7 The JVM Abstract State Machine | 346 |
References | 356 |
Citi izdevumi - Skatīt visu
Architecture Design and Validation Methods Professor of Computer Science Department of Information Egon Borger Priekšskatījums nav pieejams - 2000 |
Bieži izmantoti vārdi un frāzes
abstraction actor algorithm applied assignment behavioral synthesis Boolean functions Boolean matching buffer bytecode capacitance cells CFSM checking circuit class loader clock cluster function complexity Computer-Aided Design data flow dataflow decomposition defect defined delay Design Automation Conference dynamic embedded embedded systems equivalence example execution finite Finite State Machines floorplan formal formal verification gate global graph hardware IEEE IEEE Transactions implementation initial input instruction Java language layout synthesis LFSR loaded logic synthesis machine meth method models of computation modules node OBDD's operand stack operations optimization output path problem Proc rectangle representation represented retiming rules s₁ scan scheduling sequence shape constraints signal signature simulation slicing specification structure subroutine switch synchronous tags techniques Test Conference test pattern Test register tion transition transition relation values variables vector verification VHDL wire plan
Atsauces uz šo grāmatu
Synthesis Techniques and Optimizations for Reconfigurable Systems Ryan Kastner,Adam Kaplan,Majid Sarrafzadeh Ierobežota priekšskatīšana - 2003 |