Languages and Compilers for Parallel Computing: 19th International Workshop, LCPC 2006, New Orleans, LA, USA, November 2-4, 2006, Revised Papers

Pirmais vāks
Gheorghe Almási, George S. Almasi, Calin Cascaval, Peng Wu
Springer Science & Business Media, 2007. gada 25. maijs - 366 lappuses
The 19th Workshop on Languages and Compilers for Parallel Computing was heldinNovember2006inNewOrleans,LouisianaUSA.Morethan40researchers from around the world gathered together to present their latest results and to exchange ideas on topics ranging from parallel programming models, code generation,compilationtechniques,paralleldatastructureandparallelexecution models,toregisterallocationandmemorymanagementinparallelenvironments. Out of the 49 paper submissions, the Program Committee, with the help of external reviewers, selected 24 papers for presentation at the workshop. Each paper had at least three reviews and was extensively discussed in the comm- tee meeting. The papers were presented in 30-minute sessions at the workshop. One of the selected papers, while still included in the proceedings, was not p- sented because of an unfortunate visa problem that prevented the authors from attending the workshop. We werefortunateto havetwooutstanding keynoteaddressesatLCPC2006, both from UC Berkeley. Kathy Yelick presented “Compilation Techniques for Partitioned Global Address Space Languages.” In this keynote she discussed the issues in developing programming models for large-scale parallel machines and clusters, and how PGAS languages compare to languages emerging from the DARPA HPCS program.She also presented compiler analysis and optimi- tion techniques developed in the context of UPC and Titanium source-to-source compilers for parallel program and communication optimizations.

No grāmatas satura

Atlasītās lappuses

Saturs

Compilation Techniques for Partitioned Global Address Space Languages
1
Can Transactions Enhance Parallel Programs?
2
Design and Use of htalib A Library for Hierarchically Tiled Arrays
17
SPCE An SPBased Programming Model for Consumer Electronics Streaming Applications
33
Data Pipeline Optimization for Shared Memory MultipleSIMD Architecture
49
DependenceBased Code Generation for a CELL Processor
64
Expression and Loop Libraries for HighPerformance Code Synthesis
80
Applying Code Specialization to FFT Libraries for Integral Parameters
96
Organization
370
Table of Contents
371
Compilation Techniques for Partitioned Global Address Space Languages
1
Can Transactions Enhance Parallel Programs?
2
Design and Use of htalib A Library for Hierarchically Tiled Arrays
17
SPCE An SPBased Programming Model for Consumer Electronics Streaming Applications
33
Data Pipeline Optimization for Shared Memory MultipleSIMD Architecture
49
DependenceBased Code Generation for a CELL Processor
64

A Characterization of Shared Data Access Patterns in UPC Programs
111
Exploiting Speculative ThreadLevel Parallelism in Data Compression Applications
126
On Control Signals for MultiDimensional Time
141
A New Framework and aNew Platform for Parallel Research
156
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing
158
Iterative Compilation with Kernel Exploration
173
Quantifying Uncertainty in PointsTo Relations
190
Cache Behavior Modelling for Codes Involving Banded Matrices
205
TreeTraversal Orientation Analysis
220
An Unbalanced Tree Search Benchmark
235
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files
251
Optimal Bitwise Register Allocation Using Integer Linear Programming
267
What Does the NPCompleteness Proof of Chaitin et al Really Prove? Or Revisiting Register Allocation Why and How
283
Custom Memory Allocation for Free
299
Optimizing the Use of Static Buffers for DMA on a CELL Chip
314
Runtime Address Space Computation for SDSM Systems
330
Unified Memory Analysis The Base Framework
345
Author Index
364
Title
366
Preface
369
Expression and Loop Libraries for HighPerformance Code Synthesis
80
Applying Code Specialization to FFT Libraries for Integral Parameters
96
A Characterization of Shared Data Access Patterns in UPC Programs
111
Exploiting Speculative ThreadLevel Parallelism in Data Compression Applications
126
On Control Signals for MultiDimensional Time
141
A New Framework and aNew Platform for Parallel Research
156
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing
158
Iterative Compilation with Kernel Exploration
173
Quantifying Uncertainty in PointsTo Relations
190
Cache Behavior Modelling for Codes Involving Banded Matrices
205
TreeTraversal Orientation Analysis
220
An Unbalanced Tree Search Benchmark
235
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files
251
Optimal Bitwise Register Allocation Using Integer Linear Programming
267
What Does the NPCompleteness Proof of Chaitin et al Really Prove? Or Revisiting Register Allocation Why and How
283
Custom Memory Allocation for Free
299
Optimizing the Use of Static Buffers for DMA on a CELL Chip
314
Runtime Address Space Computation for SDSM Systems
330
Unified Memory Analysis The Base Framework
345
Author Index
364

Citi izdevumi - Skatīt visu

Bieži izmantoti vārdi un frāzes

Bibliogrāfiskā informācija