On-Chip Communication Architectures: System on Chip Interconnect

Pirmais vāks
Morgan Kaufmann, 2010. gada 28. jūl. - 544 lappuses

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.

On-Chip Communication Architecures is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

  • A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
  • Detailed analysis of all popular standards for on-chip communication architectures
  • Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
  • Future trends that with have a significant impact on research and design of communication architectures over the next several years

No grāmatas satura

 

Atlasītās lappuses

Saturs

CHAPTER 1 Introduction
1
CHAPTER 2 Basic Concepts of BusBased Communication Architectures
17
CHAPTER 3 OnChip Communication Architecture Standards
43
CHAPTER 4 Models for Performance Exploration
101
CHAPTER 5 Models for Power and Thermal Estimation
143
CHAPTER 6 Synthesis of OnChip Communication Architectures
185
CHAPTER 7 Encoding Techniques for OnChip Communication Architectures
253
CHAPTER 8 Custom BusBased OnChip Communication Architecture Design
301
CHAPTER 9 OnChip Communication Architecture Refinement and Interface Synthesis
341
CHAPTER 10 Verification and Security Issues in OnChip Communication Architecture Design
367
CHAPTER 11 Physical Design Trends for Interconnects
403
CHAPTER 12 NetworksOnChip
439
CHAPTER 13 Emerging OnChip Interconnect Technologies
473
Index
509
Autortiesības

Bieži izmantoti vārdi un frāzes

address bus AHB bus algorithm AMBA AMBA specification approach arbitration scheme bandwidth bits buffer burst bus architecture bus matrix bus topology bus width capacitance channel chip clock cycle clock distribution network clock frequency clock signal CMOS communication protocol components Computer Computer-Aided Design configuration constraints crossbar crosstalk data bus data transfer decoder Design Automation Conference design flow dynamic encoding energy estimation FIGURE IEEE IEEE Transactions implementation input integrated Integrated Circuits interconnect interface International Conference International Symposium IP core latency logic low power master memory methodology module MPSoC multiple node number of buses on-chip communication architecture optimization packet parameters performance pipelined power consumption priority processor propagation delay proposed reduce request router shared bus shown in Fig signal simulation slave SoC designs specification static STBus switching synchronous synthesis SystemC techniques tion transition verification VLSI waveguides write data

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Bibliogrāfiskā informācija

NosaukumsOn-Chip Communication Architectures: System on Chip Interconnect
AutoriSudeep Pasricha, Nikil Dutt
IzdevējsMorgan Kaufmann, 2010
ISBN0080558283, 9780080558288
Apjoms544 lappuses
  
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