... 487-492. [25] H. Qian, SR Nassif, and SS Sapatnekar, Power grid analysis using random walks, IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst., 24, 1204-1224, 2005. [26] PG Doyle and JL Snell, Random Walks and Electric Networks, Mathematical... Design for Manufacturability and Statistical Design: A Constructive Approach - 304. lappuseautors: Michael Orshansky, Sani Nassif, Duane Boning - 2007 - 316 lapasIerobežota priekšskatīšana - Par šo grāmatu
| Yoon-Soo Park, Michael Shur, William Tang - 2002 - 442 lapas
...Gigascale Integration (GSI)", Proc. IEEE Intl. Interconnect Technology Con/. (IITC), 2001, pp. 125-127. 2. R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young,...Combined Package and On-Chip Power Grid Simulation", Proc. Intl. Symp. on Low Power Electronics and Design (ISLPED), 2000, pp. 179-184. 3. P. Heydari and... | |
| Andrey V. Mezhiba, Eby G. Friedman - 2004 - 308 lapas
...IEEE Topical Meeting on Electrical Performance of Electronic Packaging, pp. 211214, October 2001. [90] R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju, "Model and Analysis of Combined Package and On-Chip Power Grid Simulation," Proceedings of the IEEE International Symposium... | |
| Sudeep Pasricha, Nikil Dutt - 2010 - 544 lapas
...Jung, U. Narayanan, CL Liu and S.-M. Kang, "Noise-aware power optimization for on-chip interconnect," in Proceedings of International Symposium on Low Power Electronics and Design, 2000, pp. 108- 1 1 3. [144] H. Zhang, V George and J. Rabaey, "Low-swing on-chip signaling techniques: Effectiveness... | |
| |