CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 21.
39. lappuse
... write . Each port access is modeled as a series of data unit accesses . A data unit access is a series of hardware data transfer operations performed without any intervening synchronization . Because they have multiple data unit ...
... write . Each port access is modeled as a series of data unit accesses . A data unit access is a series of hardware data transfer operations performed without any intervening synchronization . Because they have multiple data unit ...
44. lappuse
... write , which are asynchronous and blocking respectively . Channel ep1 has only an asynchronous read port . Channel ep2 has only a blocking write port . Channel ep1 and ep2 have pre - allocated DMA channels . The device controller ...
... write , which are asynchronous and blocking respectively . Channel ep1 has only an asynchronous read port . Channel ep2 has only a blocking write port . Channel ep1 and ep2 have pre - allocated DMA channels . The device controller ...
99. lappuse
... write to a channel if the associated FIFO is full . In the remainder of this article we will refer to this model as ... writing from these pointers . loop memory IMC IDCT 尚圆圈 Video processor Texture Motion DISP estimator input SAD ...
... write to a channel if the associated FIFO is full . In the remainder of this article we will refer to this model as ... writing from these pointers . loop memory IMC IDCT 尚圆圈 Video processor Texture Motion DISP estimator input SAD ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires