CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 27.
2. lappuse
... virtual synchronization technique to the case where multiple software tasks are executed under the supervision of a real - time operating system ( RTOS ) in a processor . Virtual synchronization cannot be directly applied in this case ...
... virtual synchronization technique to the case where multiple software tasks are executed under the supervision of a real - time operating system ( RTOS ) in a processor . Virtual synchronization cannot be directly applied in this case ...
153. lappuse
... virtual design abstraction level . The problem in measuring timing at the virtual design level is that the virtual pins are not associated with drivers and there are no buffers inserted in the virtual design floorplan . Although we can ...
... virtual design abstraction level . The problem in measuring timing at the virtual design level is that the virtual pins are not associated with drivers and there are no buffers inserted in the virtual design floorplan . Although we can ...
155. lappuse
... virtual net ( in the virtual floorplan , after global routing ) and the average wire length for all corresponding real nets in the final real layout . The results , given in Table 1 , show a good correlation between wire lengths ...
... virtual net ( in the virtual floorplan , after global routing ) and the average wire length for all corresponding real nets in the final real layout . The results , given in Table 1 , show a good correlation between wire lengths ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires