CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 67.
13. lappuse
... value in the corresponding position respectively . The ' x ' symbol matches with both 1 and 0 values . In this model , an instruction of a processor is composed of a series of slots , I = < slo , sl1 , ... > , and each slot contains ...
... value in the corresponding position respectively . The ' x ' symbol matches with both 1 and 0 values . In this model , an instruction of a processor is composed of a series of slots , I = < slo , sl1 , ... > , and each slot contains ...
15. lappuse
... value always ) and hence it is a waste of time to check the condition for such instructions every time they are executed . By considering these constant ( static ) values and applying the partial evaluation technique [ 14 ] , it is ...
... value always ) and hence it is a waste of time to check the condition for such instructions every time they are executed . By considering these constant ( static ) values and applying the partial evaluation technique [ 14 ] , it is ...
170. lappuse
... values only , as opposed to also including integer values or other types of values . We refer to such blocks as Boolean eBlocks . Boolean eBlocks presented an initial challenge of choosing the most intuitive representation of " true ...
... values only , as opposed to also including integer values or other types of values . We refer to such blocks as Boolean eBlocks . Boolean eBlocks presented an initial challenge of choosing the most intuitive representation of " true ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires