CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 50.
68. lappuse
... units 2 memory units 1 branch unit Only four units out of the given seven can be active at any time . This is very similar to the PXA250 processor , which has a general execution unit and therefore about the same amount of scheduling ...
... units 2 memory units 1 branch unit Only four units out of the given seven can be active at any time . This is very similar to the PXA250 processor , which has a general execution unit and therefore about the same amount of scheduling ...
101. lappuse
... Units CLIP DEC DISP ASU Interconnection Network / Registers files BW Standard VLW CLIP CONS compongu ALU ACU1 ACU2 MUT ROM FLAM MEMORY MEMPTR VLIW Controller ( CTRL ) MC DCTI DISP IQ ZZ RLE VLE ASU BW CLIP DCTI DEC DISP MEMPTR RND SAD ...
... Units CLIP DEC DISP ASU Interconnection Network / Registers files BW Standard VLW CLIP CONS compongu ALU ACU1 ACU2 MUT ROM FLAM MEMORY MEMPTR VLIW Controller ( CTRL ) MC DCTI DISP IQ ZZ RLE VLE ASU BW CLIP DCTI DEC DISP MEMPTR RND SAD ...
149. lappuse
... units . The resulting iteration bound is B ( G ) = 8/5 . The iteration period constraint is P 7/4 . For Allpole Filter ( " Allpole " ) , an addition operation takes 2 time units , and a multiplication operation takes 5 time units.the ...
... units . The resulting iteration bound is B ( G ) = 8/5 . The iteration period constraint is P 7/4 . For Allpole Filter ( " Allpole " ) , an addition operation takes 2 time units , and a multiplication operation takes 5 time units.the ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires