CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 86.
30. lappuse
... techniques . We have further presented a tool prototype which is able to process the proposed ex- tended synthesis subset by performing the illustrated syn- thesis techniques , and which generates SystemC or VHDL specifications that are ...
... techniques . We have further presented a tool prototype which is able to process the proposed ex- tended synthesis subset by performing the illustrated syn- thesis techniques , and which generates SystemC or VHDL specifications that are ...
96. lappuse
... techniques that have to be used in order to derive automatically KPNs from WDAS . The results , we have obtained for the MJPEG application , indicated that some optimization techniques have to be added to the approach that will help ...
... techniques that have to be used in order to derive automatically KPNs from WDAS . The results , we have obtained for the MJPEG application , indicated that some optimization techniques have to be added to the approach that will help ...
144. lappuse
... techniques . The experimental results on a set of DSP benchmarks show the ef- ficiency and effectiveness of the IDOM algorithm . It constantly generates the minimal configuration for all the benchmarks . The cost of design space ...
... techniques . The experimental results on a set of DSP benchmarks show the ef- ficiency and effectiveness of the IDOM algorithm . It constantly generates the minimal configuration for all the benchmarks . The cost of design space ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires