CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 87.
1. lappuse
... technique , called virtual synchronization , for fast and time accurate cosimulation that involves interacting component simulators . In this paper , we further extend the virtual synchronization technique with OS modeling for the case ...
... technique , called virtual synchronization , for fast and time accurate cosimulation that involves interacting component simulators . In this paper , we further extend the virtual synchronization technique with OS modeling for the case ...
136. lappuse
... technique : In contrast to the Oracle technique , we associate the buffering size with each static load / store instruction in the ABS technique as discussed above in Section 4 . We show the results for the ABS technique while comparing ...
... technique : In contrast to the Oracle technique , we associate the buffering size with each static load / store instruction in the ABS technique as discussed above in Section 4 . We show the results for the ABS technique while comparing ...
202. lappuse
... technique is given and only simulation results are presented . The work of Lee et . al . [ 7 ] performs set based analysis of the cache blocks used by the preempted task 7 before and after preemption . This is extended in [ 8 ] to also ...
... technique is given and only simulation results are presented . The work of Lee et . al . [ 7 ] performs set based analysis of the cache blocks used by the preempted task 7 before and after preemption . This is extended in [ 8 ] to also ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires