CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 72.
25. lappuse
... synthesis based on SystemC . We will give an introduction to an extended SystemC synthesis sub- set which we propose , and , in particular , its object - oriented features . We will also briefly outline our basic synthesis con- cepts ...
... synthesis based on SystemC . We will give an introduction to an extended SystemC synthesis sub- set which we propose , and , in particular , its object - oriented features . We will also briefly outline our basic synthesis con- cepts ...
28. lappuse
... SYNTHESIS BASICS In this section we will give a very brief overview of our basic synthesis concepts . More details can be found in [ 8 ] which builds the foundation of our work . The key of the synthesis concept we apply to object ...
... SYNTHESIS BASICS In this section we will give a very brief overview of our basic synthesis concepts . More details can be found in [ 8 ] which builds the foundation of our work . The key of the synthesis concept we apply to object ...
30. lappuse
... synthesis subset which is supported by existing syn- thesis tools can be simply extended by most object - oriented C ++ features , and we have proposed an appropriate synthe- sis technique for this purpose . We have also discussed how ...
... synthesis subset which is supported by existing syn- thesis tools can be simply extended by most object - oriented C ++ features , and we have proposed an appropriate synthe- sis technique for this purpose . We have also discussed how ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires