CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 31.
4. lappuse
... switch overhead . The second term of the formula is the total preemption time and the resultant context switch overhead that task i suffers by those tasks with higher priority . The accuracy of the proposed OS modeling approach depends ...
... switch overhead . The second term of the formula is the total preemption time and the resultant context switch overhead that task i suffers by those tasks with higher priority . The accuracy of the proposed OS modeling approach depends ...
36. lappuse
... switches while providing the lowest response times . Note that context switch delays in the RTOS were not modeled in this exam- ple , i.e. the large number of context switches would intro- duce additional delays that would offset the ...
... switches while providing the lowest response times . Note that context switch delays in the RTOS were not modeled in this exam- ple , i.e. the large number of context switches would intro- duce additional delays that would offset the ...
171. lappuse
... switch 3 - Input Logic Block configurable logic block programmed by the user via DIP switch Yes / No Block - outputs a constant yes or no depending on user defined setting Table 1 includes a more detailed description for a subset of ...
... switch 3 - Input Logic Block configurable logic block programmed by the user via DIP switch Yes / No Block - outputs a constant yes or no depending on user defined setting Table 1 includes a more detailed description for a subset of ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires