CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 55.
9. lappuse
... Structure After the transactions are processed by the network engine , the respective TDS is passed back to the NoC Channel with an attached tag . This tag denotes the calculated arrival time of the transaction . According to this ...
... Structure After the transactions are processed by the network engine , the respective TDS is passed back to the NoC Channel with an attached tag . This tag denotes the calculated arrival time of the transaction . According to this ...
26. lappuse
... structure of a system . Our approach focuses on data type based object - oriented modelling for mainly two reasons ; first , because of the prob- lems of the structural approaches as mentioned above , and second , because it can be ...
... structure of a system . Our approach focuses on data type based object - oriented modelling for mainly two reasons ; first , because of the prob- lems of the structural approaches as mentioned above , and second , because it can be ...
54. lappuse
... structure of the arithmetic circuits of the GF ( 2 ) processor forms the middle abstraction level in Table 1 in this paper . An Instruction Set Architecture can then be defined over this architecture which allows the processor to ...
... structure of the arithmetic circuits of the GF ( 2 ) processor forms the middle abstraction level in Table 1 in this paper . An Instruction Set Architecture can then be defined over this architecture which allows the processor to ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires