CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 48.
84. lappuse
... Static phase Dynamic phase Static phase communication controller Dynamic phase m2 T1,2 T1.4 $ 12.2 ST : T2.3 m1 , m3 T2,2 DYN : m2 , m4 DYN msg DYN msg slot 3 slot 2 slot 1 DYN msg DYN msg DYN msg slot 7 slot 6 slot 5 slot 4 Figure 1 ...
... Static phase Dynamic phase Static phase communication controller Dynamic phase m2 T1,2 T1.4 $ 12.2 ST : T2.3 m1 , m3 T2,2 DYN : m2 , m4 DYN msg DYN msg slot 3 slot 2 slot 1 DYN msg DYN msg DYN msg slot 7 slot 6 slot 5 slot 4 Figure 1 ...
135. lappuse
... static load / store instructions in the program , we average the extents observed at all dynamic instances of that static instruction . For example , Figure 8 shows average values and standard deviations of the span of buffered rows ...
... static load / store instructions in the program , we average the extents observed at all dynamic instances of that static instruction . For example , Figure 8 shows average values and standard deviations of the span of buffered rows ...
196. lappuse
... static estimation method taking into account of all dynamic behaviors due to bus contention and dynamic memory ... static estimation method based on the queuing model . Using those parameter values , the static performance estimation of ...
... static estimation method taking into account of all dynamic behaviors due to bus contention and dynamic memory ... static estimation method based on the queuing model . Using those parameter values , the static performance estimation of ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires