CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 8.
65. lappuse
... speech recognition systems traditionally executed only on high performance systems . In several ways , the needs of embedded computing differ from those of more traditional general - purpose systems . Embedded systems have more ...
... speech recognition systems traditionally executed only on high performance systems . In several ways , the needs of embedded computing differ from those of more traditional general - purpose systems . Embedded systems have more ...
66. lappuse
... Speech Recognition is a very active area of research . In addition , two main problems , accuracy and running time have been analyzed in speech recognizers executing on modern general purpose hardware . Agaram et al . [ 2,11 ] have ...
... Speech Recognition is a very active area of research . In addition , two main problems , accuracy and running time have been analyzed in speech recognizers executing on modern general purpose hardware . Agaram et al . [ 2,11 ] have ...
70. lappuse
... speech recognition systems are , too . Developing a fixed - point speech recognizer is definitely an interesting project for the future . The data used for this task are from children's speech corpus . The speech of children has a ...
... speech recognition systems are , too . Developing a fixed - point speech recognizer is definitely an interesting project for the future . The data used for this task are from children's speech corpus . The speech of children has a ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires