CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 61.
14. lappuse
... specifications containing operation or micro - operation classes . The binary stream is compared with the elements of the specification to find the specification - mask pair that matches with the beginning of the stream . The length of ...
... specifications containing operation or micro - operation classes . The binary stream is compared with the elements of the specification to find the specification - mask pair that matches with the beginning of the stream . The length of ...
177. lappuse
... specification . Transformational approaches have been used mostly for develop- ment of software programs [ 13 ] but software transformational ap- proaches do not deal with synchronous sub - domains and resource sharing which are ...
... specification . Transformational approaches have been used mostly for develop- ment of software programs [ 13 ] but software transformational ap- proaches do not deal with synchronous sub - domains and resource sharing which are ...
181. lappuse
... specification is incor- rect and gave a trace which lead to the state where the prop- erty was not satisfied . Later we increased the length of sub- streams from eight to nine and the proposed specification was true . The first ...
... specification is incor- rect and gave a trace which lead to the state where the prop- erty was not satisfied . Later we increased the length of sub- streams from eight to nine and the proposed specification was true . The first ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires