CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 73.
101. lappuse
... Specific Units CLIP DEC DISP ASU Interconnection Network / Registers files BW Standard VLW CLIP CONS compongu ALU ACU1 ACU2 MUT ROM FLAM MEMORY MEMPTR VLIW Controller ( CTRL ) MC DCTI DISP IQ ZZ RLE VLE ASU BW CLIP DCTI DEC DISP MEMPTR ...
... Specific Units CLIP DEC DISP ASU Interconnection Network / Registers files BW Standard VLW CLIP CONS compongu ALU ACU1 ACU2 MUT ROM FLAM MEMORY MEMPTR VLIW Controller ( CTRL ) MC DCTI DISP IQ ZZ RLE VLE ASU BW CLIP DCTI DEC DISP MEMPTR ...
103. lappuse
... specific systems . They combine a software programmable processor and a reconfigurable hardware component that can be reused in different applications . This combination allows reconfigurable systems to achieve performance levels ...
... specific systems . They combine a software programmable processor and a reconfigurable hardware component that can be reused in different applications . This combination allows reconfigurable systems to achieve performance levels ...
232. lappuse
... specific processors . 5 ) Embedded systems architecture Heterogeneous multiprocessors , reconfigurable platforms , memory manage- ment support , communication , protocols , network - on - chip . 6 ) Application - specific processor ...
... specific processors . 5 ) Embedded systems architecture Heterogeneous multiprocessors , reconfigurable platforms , memory manage- ment support , communication , protocols , network - on - chip . 6 ) Application - specific processor ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires