CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 65.
144. lappuse
... Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an effective way to reduce the design space to be explored through the study of the fundamental properties and ...
... Space Minimization ( IDOM ) towards finding the minimum configuration satisfying timing and code size constraints . We show an effective way to reduce the design space to be explored through the study of the fundamental properties and ...
145. lappuse
... space min- imization . Section 3 provides the algorithms and computation cost for several design space exploration algorithms . An example for design optimization and space exploration is demonstrated in Sec- tion 4 to compare the size ...
... space min- imization . Section 3 provides the algorithms and computation cost for several design space exploration algorithms . An example for design optimization and space exploration is demonstrated in Sec- tion 4 to compare the size ...
196. lappuse
... space to be explored by simulation would be narrower . The key contribution of this paper is to propose an accurate ... space exploration framework and outline the performance estimation techniques . Section 3 reviews some related works ...
... space to be explored by simulation would be narrower . The key contribution of this paper is to propose an accurate ... space exploration framework and outline the performance estimation techniques . Section 3 reviews some related works ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires