CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 88.
5. lappuse
... shows the performance improvement due to OS modeling itself . Simulation was performed with cache enabled and with the corresponding timing constraints defined in Table 1. For eCOS simulation , using the equation ( 5.2 ) , the expected ...
... shows the performance improvement due to OS modeling itself . Simulation was performed with cache enabled and with the corresponding timing constraints defined in Table 1. For eCOS simulation , using the equation ( 5.2 ) , the expected ...
136. lappuse
... shows how well this could be practically achieved . Figure 9 shows the variation of the spatial locality in the different applications . These results were obtained by mon- itoring the access behavior of the buffered DRAM row that was ...
... shows how well this could be practically achieved . Figure 9 shows the variation of the spatial locality in the different applications . These results were obtained by mon- itoring the access behavior of the buffered DRAM row that was ...
214. lappuse
... shows that the three proposed approaches provide significant savings in leakage energy consumption . The remainder of this paper is organized as follows . In the next section , we introduce our experimental setup and the benchmark suite ...
... shows that the three proposed approaches provide significant savings in leakage energy consumption . The remainder of this paper is organized as follows . In the next section , we introduce our experimental setup and the benchmark suite ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires