CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 86.
94. lappuse
... shown in Figure 3. The corresponding sched- ule tree ( STree ) is depicted at the top part of Figure 4 - c ) . If we parse this tree top - down from left to right a program can be generated that gives a valid execution order ( global ...
... shown in Figure 3. The corresponding sched- ule tree ( STree ) is depicted at the top part of Figure 4 - c ) . If we parse this tree top - down from left to right a program can be generated that gives a valid execution order ( global ...
173. lappuse
... shown in Table 1 , a cafeteria manager can design a simple system for service line workers to indicate to kitchen staff which food items need replenishing . As shown in Figure 3 ( b ) , we start by placing an LED and button pair by the ...
... shown in Table 1 , a cafeteria manager can design a simple system for service line workers to indicate to kitchen staff which food items need replenishing . As shown in Figure 3 ( b ) , we start by placing an LED and button pair by the ...
220. lappuse
... shown in figure 2 , box ( 4 ) . Only the decla- rations of D and B are shown to simplify presentation of the later transformation stages . We now need to generate a separate program for each pro- cessor . The partitioned code for ...
... shown in figure 2 , box ( 4 ) . Only the decla- rations of D and B are shown to simplify presentation of the later transformation stages . We now need to generate a separate program for each pro- cessor . The partitioned code for ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires