CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 41.
193. lappuse
... scheme is guided by reliability and bandwidth constraints . Parameters are the number of parallel encoded blocks and their interleaving degree . This trade - off is shown in table 4. Out of these coding schemes , the appropriate one can ...
... scheme is guided by reliability and bandwidth constraints . Parameters are the number of parallel encoded blocks and their interleaving degree . This trade - off is shown in table 4. Out of these coding schemes , the appropriate one can ...
214. lappuse
... scheme can turn off cache lines much earlier than the garbage collector . How- ever , only method local objects can benefit from this scheme . Our third technique attempts to be even more precise . We identify the last - use of the ...
... scheme can turn off cache lines much earlier than the garbage collector . How- ever , only method local objects can benefit from this scheme . Our third technique attempts to be even more precise . We identify the last - use of the ...
218. lappuse
... scheme is also used . ) advantage of this scheme is that it has more chances to turn off cache lines . However , it also introduces extra cache misses since we may turn off the RCLs of some of objects that may be used in the near future ...
... scheme is also used . ) advantage of this scheme is that it has more chances to turn off cache lines . However , it also introduces extra cache misses since we may turn off the RCLs of some of objects that may be used in the near future ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires