CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 61.
32. lappuse
... scheduling and dynamic scheduling in software synthesis is proposed . While both approaches mainly focus on software synthesis issues , their papers do not provide any information regarding high level model of dynamic schedul- ing ...
... scheduling and dynamic scheduling in software synthesis is proposed . While both approaches mainly focus on software synthesis issues , their papers do not provide any information regarding high level model of dynamic schedul- ing ...
115. lappuse
... scheduling is a combination of quasi- static scheduling and dynamic scheduling . Data dependent branch executions are statically decomposed into different behavior con- figurations and quasi - statically scheduled [ 17 ] . For each ...
... scheduling is a combination of quasi- static scheduling and dynamic scheduling . Data dependent branch executions are statically decomposed into different behavior con- figurations and quasi - statically scheduled [ 17 ] . For each ...
122. lappuse
... scheduling of the above problem for 1000 frames . In each frame the task graphs are selected randomly and the time constraint is always 3.4ms . The re- sults are shown in Tab . 2 , in which our two - Vdd scheduler en . cons . ( uJ ) en ...
... scheduling of the above problem for 1000 frames . In each frame the task graphs are selected randomly and the time constraint is always 3.4ms . The re- sults are shown in Tab . 2 , in which our two - Vdd scheduler en . cons . ( uJ ) en ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires