CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 9.
75. lappuse
... scaling properties of wires and gates are at the center of this phenomenon . It is true that those wires that scale in length together with gate lengths present approxi- mately a constant resistance and a falling capacitance . However ...
... scaling properties of wires and gates are at the center of this phenomenon . It is true that those wires that scale in length together with gate lengths present approxi- mately a constant resistance and a falling capacitance . However ...
189. lappuse
... scaling also gives rise to new error sources : For instance can the effects of neutrons ( which have formerly only been a concern with memories ) now cause upsets in logic elements and low power / low capacitance buses as well [ 9 ] ...
... scaling also gives rise to new error sources : For instance can the effects of neutrons ( which have formerly only been a concern with memories ) now cause upsets in logic elements and low power / low capacitance buses as well [ 9 ] ...
194. lappuse
... scaling and the industry's ability to benefit from it . The complexity of process and design technology , its impact on new designs , new products development and future solutions will be discussed in this presentation . Biography Mr ...
... scaling and the industry's ability to benefit from it . The complexity of process and design technology , its impact on new designs , new products development and future solutions will be discussed in this presentation . Biography Mr ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires