CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 23.
40. lappuse
... Request functions can overlap because a request function takes several transitions to complete and events are visible at the states . Five policies to coordinate two requests of the different types , and different instances of the same ...
... Request functions can overlap because a request function takes several transitions to complete and events are visible at the states . Five policies to coordinate two requests of the different types , and different instances of the same ...
41. lappuse
... request , interrupt request , and asynchronous input . A timer event occurs when the timer expires . An interrupt request event occurs when an interrupt needs to be serviced . A task request event is emitted when a task , user ( or ...
... request , interrupt request , and asynchronous input . A timer event occurs when the timer expires . An interrupt request event occurs when an interrupt needs to be serviced . A task request event is emitted when a task , user ( or ...
43. lappuse
... request if it is a request ; Event process kernel ( a kernel thread ) : For each state machine { } For each event { if ( enabled transitions exist ) Fire it ; Enqueue the output events ; Delete the enabling event ; Unblock a request ...
... request if it is a request ; Event process kernel ( a kernel thread ) : For each state machine { } For each event { if ( enabled transitions exist ) Fire it ; Enqueue the output events ; Delete the enabling event ; Unblock a request ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
19 citas sadaļas nav parādītas.
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires