CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 64.
20. lappuse
... represents computation and y - axis represents com- munication . On each axis , we have three degrees of time accuracy : un - timed , approximate - timed , and cycle - timed . Un - timed computation / communication represents the pure ...
... represents computation and y - axis represents com- munication . On each axis , we have three degrees of time accuracy : un - timed , approximate - timed , and cycle - timed . Un - timed computation / communication represents the pure ...
116. lappuse
... represents a subtask . Thus , a wider domain of ap- plications can be precisely modeled by RTPN . Details on the ... represents a marking with a corresponding set of concurrently enabled transitions and each edge represents the firing of ...
... represents a subtask . Thus , a wider domain of ap- plications can be precisely modeled by RTPN . Details on the ... represents a marking with a corresponding set of concurrently enabled transitions and each edge represents the firing of ...
164. lappuse
... represents a 1 bit output from a LFSR with seed s ( or it is clocked for y cycles if a y - bit output is implied in the formula ) ; { } m - x .. m represent the last x bits of a m - bit quantity in brackets ; let + represent exclusive ...
... represents a 1 bit output from a LFSR with seed s ( or it is clocked for y cycles if a y - bit output is implied in the formula ) ; { } m - x .. m represent the last x bits of a m - bit quantity in brackets ; let + represent exclusive ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires