CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 26.
23. lappuse
Synthesis domain Exploration domain Refinement domain Modeling domain Validation domain O 아 Estimation Synthesis Design decisions Refinement Model A Simulation Verification Model B 3. Component attribute library 2. Estimation library 1 ...
Synthesis domain Exploration domain Refinement domain Modeling domain Validation domain O 아 Estimation Synthesis Design decisions Refinement Model A Simulation Verification Model B 3. Component attribute library 2. Estimation library 1 ...
33. lappuse
... Refinement Decisions Task fork ( ) ; void join ( Task t ) ; / * Event handling * / T1 PE PE Bus driver read Task ... refinement tool B2 Figure 3 : Interface of the RTOS model B1 C1 B3 C2 PE Bus driver Run Time Environment Task PE 81 C1 ...
... Refinement Decisions Task fork ( ) ; void join ( Task t ) ; / * Event handling * / T1 PE PE Bus driver read Task ... refinement tool B2 Figure 3 : Interface of the RTOS model B1 C1 B3 C2 PE Bus driver Run Time Environment Task PE 81 C1 ...
36. lappuse
... refinement tool in the design of a voice codec for mobile phone applications . The vocoder contains two tasks for encoding and decoding in software , assisted by a custom hardware co - processor . For the im- plementation , the Vocoder ...
... refinement tool in the design of a voice codec for mobile phone applications . The vocoder contains two tasks for encoding and decoding in software , assisted by a custom hardware co - processor . For the im- plementation , the Vocoder ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
Autortiesības | |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires