CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.3. rezultāts no 57.
27. lappuse
... reference that may refer to objects of different classes is dynamically bound2 to a concrete implementation at runtime , dependent on the class of the object actually being referenced . Whoever requests this operation does not have to ...
... reference that may refer to objects of different classes is dynamically bound2 to a concrete implementation at runtime , dependent on the class of the object actually being referenced . Whoever requests this operation does not have to ...
47. lappuse
Figure 1. Reference RTM Data Structure The reference RTM architecture has 64 records . The status , priority and event ID fields are each 8 bits wide and the delay field is 16 bits wide . Each record uses 40 bits of storage but is ...
Figure 1. Reference RTM Data Structure The reference RTM architecture has 64 records . The status , priority and event ID fields are each 8 bits wide and the delay field is 16 bits wide . Each record uses 40 bits of storage but is ...
217. lappuse
... reference register right after each execution of the bytecode that has been marked as potential last use site in step 1. Note that this register is shared by all potential last use sites . Fur- ther , associated with each static ...
... reference register right after each execution of the bytecode that has been marked as potential last use site in step 1. Note that this register is shared by all potential last use sites . Fur- ther , associated with each static ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires