CODES+ISSSACM Press, 2003 |
No grāmatas satura
1.–3. rezultāts no 18.
59. lappuse
... reconfigurable computation platform , which is targeting on streamed applications such as multimedia and DSP . Numerous modifications of the first - generation of the architecture have made a scalable computation and communication ...
... reconfigurable computation platform , which is targeting on streamed applications such as multimedia and DSP . Numerous modifications of the first - generation of the architecture have made a scalable computation and communication ...
103. lappuse
... Reconfigurable DSP Core 51 kbits / s 600 bits per 10ms 510 bits. Behzad Mohebbi , Eliseu Chavez Filho , Rafael Maestre , Mark Davies Morpho Technologies Inc 19772 Mac Arthur Blvd , Irvine , CA 92612 { behzad , ecf , rafael , mdavies}@ ...
... Reconfigurable DSP Core 51 kbits / s 600 bits per 10ms 510 bits. Behzad Mohebbi , Eliseu Chavez Filho , Rafael Maestre , Mark Davies Morpho Technologies Inc 19772 Mac Arthur Blvd , Irvine , CA 92612 { behzad , ecf , rafael , mdavies}@ ...
104. lappuse
... Reconfigurable DSP ( rDSP ) solutions based on a reconfigurable array processing paradigm , known as MS1 rDSP , which is briefly discussed here . As in conventional reconfigurable systems [ 1 ] , the MS1 Core contains a reconfigurable ...
... Reconfigurable DSP ( rDSP ) solutions based on a reconfigurable array processing paradigm , known as MS1 rDSP , which is briefly discussed here . As in conventional reconfigurable systems [ 1 ] , the MS1 Core contains a reconfigurable ...
Saturs
An Efficient Retargetable Framework for InstructionSet Simulation | 13 |
Extending the SystemC Synthesis Subset by ObjectOriented Features | 25 |
Hardware Support for Realtime Operating Systems | 45 |
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abstraction adiabatic circuits algorithm analysis application approach architecture behavior buffer bytecode cache blocks cache line channel chip clock Codesign communication components computation configuration constraints core cycle decoder defined delay design space exploration device device driver DRAM DRAM row dynamic EMAC embedded systems encoder energy error estimation event example execution FIFO flash memory function global hardware IEEE implementation input instruction interface iteration Kahn Process Network latency logic minimization loop M-JPEG mapping methodology module multiple NAND Nash equilibrium Newport Beach node on-chip on-memory cache optimization output overhead packet parallel parameters partitioning performance priority Proc process network processor protocol real-time retiming RTOS model RTPN scheduling Section shown in Figure simulation solution specification speech recognition static step synchronization synthesis system level SystemC Table task graphs TCP/IP technique Technology tion TLMs tool VHDL virtual VLIW wires